One of the basic digital devices used in digital circuit design is the master-slave flip-flop. In a master-slave flip-flop, the output binary state of the slave segment is intended to change to match the input binary state of the master segment upon receipt of an external clocking signal. Associated with each output state change of a master segment is a condition of state uncertainty. This condition, typically referred to as a metastable state condition, arises from minimal differences in output voltage levels between typically paired output terminal levels and the defined binary voltage levels, particularly during master output state transition between the defined output levels. It is desirable to minimize the transition time between ambiguous output levels of the master segment in order to reduce the probability that the paired inputs to the slave segment might both be driven toward the same state causing the slave segment to latch to an improper or non-intended binary state. This problem is particularly acute under rapid clock cycling conditions, i.e., at high clock edge rates.
In the prior art, two techniques have been employed to reduce the probability of latch malfunction due to the metastable state during transition of states of the master segment. The first technique has been to electrically speed up the rate of transition of the circuit elements of the master segment. This has been accomplished by using more current to drive the circuit elements of the master segment, thereby overcoming inherent or parasitic capacitance effects which would otherwise retard transition.
The second technique has been to reduce the exposure time, i.e., the time during which the state is considered valid. This is accomplished by assuring an adequate delay between the initiation of a transition in the master segment and the initiation of a clock signal level change, thereby giving the master segment transition a greater proportion of a clock cycle to settle.
Both of these techniques have inherent drawbacks. Timing delays, constraints and limitations are unwanted, and any increase in power consumption is undesirable, particularly in applications wherein the device forms a subcircuit of a larger integrated circuit. What is therefore needed is a master-slave flip-flop device which is not as subject to such inherent physical limitations on device speed.